Delta-sigma modulation

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The Delta-Sigma (ΔΣ; or sigma-delta, ΣΔ) modulation is a method for encoding high resolution signals into lower resolution signals using pulse-density modulation. This technique has found increasing use in a range of modern electronic components, such as analog-to-digital and digital-to-analog converters, frequency synthesizers, switched-mode power supplies and motor controls. One of the earliest and most widespread uses of delta-sigma modulation is in data conversion. An ADC or DAC circuit which implements this technique can relatively easily achieve very high resolutions while using low-cost CMOS processes, such as the processes used to produce digital integrated circuits; for this reason, even though it was first presented in the early 1960s, it is only in recent years that it has come into widespread use with improvements in silicon technology. Almost all analog integrated circuit vendors offer delta-sigma converters.


[edit] Analog to Digital Conversion

For the analog to digital converter, (ADC), the method can be thought of as a voltage-controlled oscillator, where the controlling voltage is the voltage to be measured and where linearity and proportionality are determined by a negative feedback loop.

The output of the oscillator is a pulse stream, each pulse of which is a known, constant, amplitude = V and duration dt and thus has a known integral = Vdt but variable separating interval. The interval between pulses is determined by the feedback loop so that a low input voltage produces a long interval between pulses and a high input voltage produces a short interval between pulses. In fact, neglecting switching errors, the interval between pulses is proportional to the inverse of the mean of the input voltage during that interval and thus over that interval, ts, is a sample of the mean of the input voltage proportional to V/ts. The feedback loop is arranged so that the integral of the input voltage is matched within one count by the integral of the pulse stream.

The output count finally produced is the digitization of the input voltage determined by counting the pulses produced in the way described above in a fixed summing interval = Ndt producing a count, Σ. The integral of the pulse stream is ΣVdt which is produced over an interval Ndt and thus the average of the input voltage over the summing period is VΣ/N and is the mean of means and so subject to little variance. The accuracy achieved depends on the accuracy with which V is known and the precision or resolution is within one count in N.

Variations in scaling can be produced by either varying the fixed summing interval, Ndt or by counting down the pulses by a fixed ratio or both methods can be used.

The pulses described above may be treated as the Dirac δ (delta) function in a formal analysis and the count as Σ (sigma).It is these pulses which are transmitted for delta-sigma modulation but are counted to form sigma in the case of analogue to digital conversion.

Fig. 1: Block diagram and waveforms for a Delta Sigma ADC.
Fig. 1a: Effect of clocking impulses

Figure 1 is a simplified block diagram of the Delta Sigma analogue to digital converter.

Shown below the block diagram are waveforms at points designated by numbers 1 to 5 for an input of 0.2 volts on the left and 0.4 volts on the right.

In most practical applications the summing interval is large compared with the impulse duration and for signals which are a significant fraction of full scale the variable separating interval is also small compared with the summing interval. The Nyquist–Shannon sampling theorem requires two samples to render a varying input signal. The samples appropriate to this criterion are two successive Σ counts taken in two successive summing intervals. The summing interval, which must accommodate a large count in order to achieve adequate precision, is inevitably long so that the converter can only render relatively low frequencies. Hence it is convenient and fair to represent the input voltage (1) as constant over a few impulses.

Consider first the waveforms on the left.

1 is the input and for this short interval is constant at 0.2V. The stream of delta impulses is shown at 2 and the difference between 1 and 2 is shown at 3. This difference is integrated to produce the waveform 4. The threshold detector generates a pulse 5 which starts as the waveform 4 crosses the threshold and is sustained until the waveform 4 falls below the threshold. Within the loop 5 triggers the impulse generator and external to the loop increments the counter. The summing interval is a prefixed time and at its expiry the count is strobed into the buffer and the counter reset.

It is necessary that the ratio between the impulse interval and the summing interval is equal to the maximum (full scale) count. It is then possible for the impulse duration and the summing interval to be defined by the same clock with a suitable arrangement of logic and counters. This has the advantage that neither interval has to be defined with absolute precision as only the ratio is important. Then to achieve overall accuracy it is only necessary that the amplitude of the impulse be accurately defined.

On the right the input is now 0.4V and the sum during the impulse is -0.6V as opposed to -0.8V on the left. Thus the negative slope during the impulse is lower on the right than on the left.

Also the sum is 0.4V on the right during the interval as opposed to 0.2V on the left. Thus the positive slope outside the impulse is higher on the right than on the left.

The resultant effect is that the integral (4) crosses the threshold more quickly on the right than on the left. A full analysis would show that in fact the interval between threshold crossings on the right is half that on the left. Thus the frequency of impulses is doubled. Hence the count increments at twice the speed on the right to that on the left which is consistent with the input voltage being doubled.

Construction of the waveforms illustrated at (4) is aided by concepts associated with the Dirac delta function in that all impulses of the same strength produce the same step when integrated, by definition. Then (4) is constructed using an intermediate step (6) in which each integrated impulse is represented by a step of the assigned strength which decays to zero at the rate determined by the input voltage. The effect of the finite duration of the impulse is constructed in (4) by drawing a line from the base of the impulse step at zero volts to intersect the decay line from (6) at the full duration of the impulse.

As stated, Fig. 1 is a simplified block diagram of the Delta-Sigma ADC in which the various functional elements have been separated out for individual treatment and which tries to be independent of any particular implementation. Many particular implementations seek to define the impulse duration and the summing interval from the same clock as discussed above but in such a way that the start of the impulse is delayed until the next occurrence of the appropriate clock pulse boundary. The effect of this delay is illustrated in Fig. 1a for a sequence of impulses which occur at a nominal 2.5 clock intervals, firstly for impulses generated immediately the threshold is crossed as previously discussed and secondly for impulses delayed by the clock. The effect of the delay is firstly that the ramp continues until the onset of the impulse, secondly that the impulse produces a fixed amplitude step so that the integral retains the excess it acquired during the impulse delay and so the ramp restarts from a higher point and is now on the same locus as the unclocked integral. The effect is that, for this example, the undelayed impulses will occur at clock points 0, 2.5, 5, 7.5, 10 etc. and the clocked impulses will occur at 0, 3, 5, 8, 10 etc. The maximum error that can occur due to clocking is marginally less than one count.

Fig. 1b: Circuit Diagram
Fig. 1c: ADC waveforms

A circuit diagram for a practical implementation is illustrated, Fig 1b and the associated waveforms Fig 1c. A scrap view of an alternative front end is shown in Fig 1b which has the advantage that the voltage at the switch terminals are relatively constant and close to 0.0V. Also the current generated through R by -Vref is constant at -Vref/R so that much less noise is radiated to adjacent parts of the circuit. Then this would be the preferred front end in practice but, in order to show the impulse as a voltage pulse so as to be consistent with previous discussion, the front end given here, which is an electrical equivalent, is used.

From the top of Fig 1c the waveforms, labeled as they are on the circuit diagram, are:-

The clock.

(a) Vin. This is shown as varying from 0.4V initially to 1.0V and then to zero volts to show the effect on the feedback loop.

(b) The impulse waveform. It will be discovered how this acquires its form as we traverse the feedback loop.

(c) The current into the capacitor, Ic, is the linear sum of the impulse voltage upon R and Vin upon R. To show this sum as a voltage the product R * Ic is plotted. The input impedance of the amplifier is regarded as so high that the current drawn by the input is neglected.

(d) The negated integral of Ic. This negation is standard for the Op.amp implementation of an integrator and comes about because the current into the capacitor at the amplifier input is the current out of the capacitor at the amplifier output and the voltage is the integral of the current divided by the capacitance of C.

(e) The comparator output. The comparator is a very high gain amplifier with its plus input terminal connected for reference to 0.0V. Whenever the negative input terminal is taken negative with respect the positive terminal of the amplifier the output saturates positive and conversely negative saturation for positive input. Thus the output saturates positive whenever the integral (d) goes below the 0V reference level and remains there until (d) goes positive with respect to the reference level.

(f) The impulse timer is a D type positive edge triggered flip flop. Input information applied at D is transferred to Q on the occurrence of the positive edge of the clock pulse. thus when the comparator output (e) is positive Q goes positive or remains positive at the next positive clock edge. Similarly, when (e) is negative Q goes negative at the next positive clock edge. Q controls the electronic switch to generate the current impulse into the integrator. Examination of the waveform (e) during the initial period illustrated, when Vin is 0.4V, shows (e) crossing the threshold well before the trigger edge so that there is an appreciable delay before the impulse starts. After the start of the impulse there is further delay while (e) climbs back past the threshold. During this time the comparator output remains high but goes low before the next trigger edge. At that next trigger edge the impulse timer goes low to follow the comparator. Thus the clock determines the duration of the impulse. For the next impulse the threshold is crossed immediately before the trigger edge and so the comparator is only briefly positive.Vin (a) goes to full scale, +Vref, shortly before the end of the next impulse. For the remainder of that impulse the capacitor current (c) goes to zero and hence the integrator slope briefly goes to zero. Following this impulse the full scale positive current is flowing (c) and the integrator sinks at its maximum rate and so crosses the threshold well before the next trigger edge. At that edge the impulse starts and the Vin current is now matched by the reference current so that the net capacitor current (c) is zero. Then the integration now has zero slope and remains at the negative value it had at the start of the impulse. This has the effect that the impulse current remains switched on because Q is stuck positive because the comparator is stuck positive at every trigger edge. This is consistent with contiguous, butting impulses which is required at full scale input. Eventually Vin (a) goes to zero which means that the current sum (c) goes fully negative and the integral ramps up. It shortly thereafter crosses the threshold and this in turn is followed by Q, thus switching the impulse current off. The capacitor current (c) is now zero and so the integral slope is zero, remaining constant at the value it had acquired at the end of the impulse.

(g) The countstream is generated by gating the negated clock with Q to produce this waveform. thereafter the summing interval, sigma count and buffered count are produced using appropriate counters and registers. The Vin waveform is approximated by passing the countstream (g) into a low pass filter, however it suffers from the defect discussed in the context of Fig_1a. One possibility for reducing this error is to halve the feedback pulse length to half a clock period and double its amplitude by halving the impulse defining resistor thus producing an impulse of the same strength but one which never butts onto its adjacent impulses. Then there will be a threshold crossing for every impulse. In this arrangement a monostable flip flop triggered by the comparator at the threshold crossing will closely follow the threshold crossings and thus eliminate one source of error, both in the ADC and the sigma delta modulator.

NB In this section we have mainly dealt with the analogue to digital converter as a stand alone function which achieves astonishing accuracy with what is now a very simple and cheap architecture. Initially the Delta-Sigma configuration was devised by INOSE et al. to solve problems in the accurate transmission of analog signals. In that application it was the pulse stream that was transmitted and the original analog signal recovered with a low pass filter after the received pulses had been reformed. This low pass filter performed the summation function associated with Σ. The highly mathematical treatment of transmission errors was introduced by them and is appropriate when applied to the pulse stream but these errors are lost in the accumulation process associated with Σ to be replaced with the errors associated with the mean of means when discussing the ADC. For those uncomfortable with this assertion consider this.

It is well known that by Fourier analysis techniques the incoming waveform can be represented over the summing interval by the sum of a constant plus a fundamental and harmonics each of which has an exact integer number of cycles over the sampling period. It is also well known that the integral of a sine wave or cosine wave over one or more full cycles is zero. Then the integral of incoming waveform over the summing interval reduces to the integral of the constant and when that integral is divided by the summing interval it becomes the mean over that interval. The interval between pulses is proportional to the inverse of the mean of the input voltage during that interval and thus over that interval, ts, is a sample of the mean of the input voltage proportional to V/ts. Thus the average of the input voltage over the summing period is VΣ/N and is the mean of means and so subject to little variance. Unfortunately the analysis for the transmitted pulse stream has, in many cases, been carried over, uncritically, to the ADC.

A very accurate transmission system with constant sampling rate may be formed using the full arrangement shown here by transmitting the samples from the buffer protected with redundancy error correction. In this case there will be a trade off between bandwidth and N, the size of the buffer. The signal recovery system will require reduncy error checking, digital to analog conversion,and sample and hold circuitry. A possible further enhancement is to include some form of slope regeneration.

NB2. The above description shows why the impulse is called delta. The integral of an impulse is a step. A one bit DAC may be expected to produce a step and so must be a conflation of an impulse and an integration. The analysis which treats the impulse as the output of a 1 bit DAC hides the structure behind the name (sigma delta) and cause confusion and difficulty interpreting the name as an indication of function. This analysis is very widespread but is deprecated.

[edit] Digital to Analog Conversion

The digital to analog converter (DAC) arrangement can be thought of as open loop with a counter, Sigma, which is preloaded with the number to be converted. The counter is counted down to zero by a series of impulses, delta. As above these impulses are of fixed amplitude and duration. At the start an integrator is set to zero and then integrates the impulses to form the analog voltage equivalent of the starting number.

[edit] Relationship to Δ-modulation

Fig. 2: Derivation of ΔΣ- from Δ-modulation

ΔΣ modulation (SDM) is inspired by Δ modulation (DM), as shown in Fig. 2. If quantization was homogeneous (e.g., if it was linear), the following would be a sufficient derivation of the equivalence of DM and SDM:

  1. Start with a block diagram of a Δ-modulator/demodulator.
  2. The linearity property of integration (\int a + \int b = \int (a + b)) makes it possible to move the integrator, which reconstructs the analog signal in the demodulator section, in front of the Δ-modulator.
  3. Again, the linearity property of the integration allows the two integrators to be combined and a ΔΣ-modulator/demodulator block diagram is obtained.

However, the quantizer is not homogeneous, and so this explanation is flawed. It's true that ΔΣ is inspired by Δ-modulation, but the two are distinct in operation. From the first block diagram in Fig. 2, the integrator in the feedback path can be removed if the feedback is taken directly from the input of the low-pass filter. Hence, for delta modulation of input signal u, the low-pass filter sees the signal

y_\text{DM} = \int \operatorname{Quantize}\left( u - y_\text{DM} \right).\,

However, sigma-delta modulation of the same input signal places at the low-pass filter

y_\text{SDM} = \operatorname{Quantize}\left( \int\left( u - y_\text{SDM} \right)\right).\,

In other words, SDM and DM swap the position of the integrator and quantizer. The net effect is a simpler implementation that has the added benefit of shaping the quantization noise away from signals of interest (i.e., signals of interest are low-pass filtered while quantization noise is high-pass filtered). This effect becomes more dramatic with increased oversampling, which allows for quantization noise to be somewhat programmable. On the other hand, Δ-modulation shapes both noise and signal equally.

Additionally, the quantizer (e.g., comparator) used in DM has a small output representing a small step up and down the quantized approximation of the input while the quantizer used in SDM must take values outside of the range of the input signal, as shown in Fig. 3.

Fig. 3: An example of SDM of 100 samples of one period a sine wave. 1-bit samples (e.g., comparator output) overlaid with sine wave where logic high (e.g., + VCC) represented by blue and logic low (e.g., VCC) represented by white.

In general, ΔΣ has some advantages versus Δ modulation:

  • The whole structure is simpler:
    • Only one integrator is needed
    • The demodulator can be a simple linear filter (e.g., RC or LC filter) to reconstruct the signal
    • The quantizer (e.g., comparator) can have full-scale outputs
  • The quantized value is the integral of the difference signal, which makes it less sensitive to the rate of change of the signal.

[edit] Principle

The principle of the ΔΣ architecture is to make rough evaluations of the signal, to measure the error, integrate it and then compensate for that error. The mean output value is then equal to the mean input value if the integral of the error is finite. A demonstration applet is available online to simulate the whole architecture. [1]

Fig. 4: Block diagram of a 2nd order ΔΣ modulator

The number of integrators, and consequently, the numbers of feedback loops, indicates the order of a ΔΣ-modulator; a 2nd order ΔΣ modulator is shown in Fig. 4. First order modulators are stable, but for higher order ones stability must be taken into great account.

The modulator can also be classified by the number of bits it has in output, which strictly depends on the output of the quantizer. The quantizer can be realized with a N-level comparator, thus the modulator has log2N-bit output; for instance, a 1-bit modulator has a quantizer realized as a simple 2-level comparator (a comparator referred to 0), whose output is 1 or 0 if the input signal is positive or negative.

[edit] Quantization theory formulas

When a signal is quantized, the resulting signal approximately has the second-order statistics of a signal with independent additive white noise. Assuming that the signal value is in the range of one step of the quantized value with an equal distribution, the root mean square value of this quantization noise is

e_\mathrm{rms}\, =\sqrt{\, \frac{1}{\Delta}\int_{-\Delta/2}^{+\Delta/2} e^2\, de\, }=\, \frac{\Delta}{\sqrt{12}}

In reality, the quantization noise is of course not independent of the signal; this dependence is the source of idle tones and pattern noise in Sigma-Delta converters.

Oversampling ratio, where fs is the sampling frequency and 2f0 is Nyquist rate


The rms noise voltage within the band of interest can be expressed in terms of OSR

\mathrm{n_0}\,=\, \frac{e_{rms}}{\sqrt{OSR}}

[edit] Structures

The MASH (Multi-stAge noise SHaping) structure has a noise shaping property, and is commonly used in digital audio and fractional-N frequency synthesizers. It comprises two or more cascaded overflowing accumulators, each of which is equivalent to a first-order sigma delta modulator. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. Besides its noise shaping function, it has two more attractive properties:

  • simple to implement in hardware; only common digital blocks such as accumulators, adders, and D flip-flops are required
  • unconditionally stable (there are no feedback loops outside the accumulators)

[edit] Oversampling

Fig. 5: Noise shaping curves and noise spectrum in ΔΣ modulator

Let's consider a signal at frequency f0 and a sampling frequency of fs much higher than Nyquist rate (see Fig. 5). ΔΣ modulation is based on the technique of oversampling to reduce the noise in the band of interest (green), which also avoids the use of high-precision analog circuits for the anti-aliasing filter. The quantization noise is the same both in a Nyquist converter (in yellow) and in an oversampling converter (in blue), but it is distributed over a larger spectrum. In ΔΣ-converters, noise is further reduced at low frequencies, which is the band where the signal of interest is, and it is increased at the higher frequencies, where it can be filtered. This property is known as noise shaping.

For a first order delta sigma modulator, the noise is shaped by a filter with transfer function H_n(z) = \left[1 - z^{-1}\right] . Assuming that the sampling frequency fs > > f0, the quantization noise in the desired signal bandwidth can be approximated as:

 \mathrm{n_0}\,=\, e_{rms}\frac{ \pi}{\sqrt{3}}\, (2f_0\tau)^{(\frac{3}{2})} .

Similarly for a second order delta sigma modulator, the noise is shaped by a filter with transfer function H_n(z) = \left[1 - z^{-1}\right]^2. The in-band quantization noise can be approximated as:

\mathrm{n_0}\,=\, e_{rms}\frac{ \pi^2}{\sqrt{5}}\, (2f_0\tau)^{(\frac{5}{2})} .

In general, for a N-order ΔΣ-modulator, the variance of the in-band quantization noise:

\mathrm{n_0}\,=\, e_{rms}\frac{\pi^n}{\sqrt{2n + 1}}\, (2f_0\tau)^{(\frac{2n + 1}{2})}.

When the sampling frequency is doubled, the signal to quantization noise is improved by 10log(22N + 1)dB for a N-order ΔΣ-modulator. Higher the oversampling ratio, the higher the signal-to-noise ratio and the higher the resolution in bits.

Another key aspect given by oversampling is the speed/resolution tradeoff. In fact, the decimation filter put after the modulator not only filters the whole sampled signal in the band of interest (cutting the noise at higher frequencies), but also reduces the frequency of the signal increasing its resolution. This is obtained by a sort of averaging of the higher data rate bitstream.

[edit] Example of decimation

Let's have, for instance, an 8:1 decimation filter and a 1-bit bitstream; if we have an input stream like 10010110, counting the number of ones, the decimation result is 4/8 = 0.5 = 100 in binary; in other words,

  • the sample frequency is reduced by a factor of eight
  • the serial (1-bit) input bus becomes a parallel (3-bits) output bus.

[edit] Naming

The name Delta-Sigma comes directly from the presence of a Delta modulator and an integrator, as firstly introduced by Inose et al. in their patent application.[2]. That is, the name comes from integrating or "summing" differences, which are operations usually associated with Greek letters Sigma and Delta respectively. Both names Sigma-Delta and Delta-Sigma are frequently used.

[edit] Applications

[edit] Notes

  1. ^ Analog Devices : Virtual Design Center : Interactive Design Tools : Sigma-Delta ADC Tutorial
  2. ^ H. Inose, Y. Yasuda, J. Murakami, "A Telemetering System by Code Manipulation -- ΔΣ Modulation," IRE Trans on Space Electronics and Telemetry, Sep. 1962, pp. 204-209.

[edit] See also

[edit] External links

[edit] Bibliography

  • R. Schreier, G. Temes (2005). Understanding Delta-Sigma Data Converters. ISBN 0-471-46585-2. 
  • R. Jacob Baker (2009). CMOS Mixed-Signal Circuit Design, Second Edition.
  • J. Candy, G. Temes (1992). Oversampling Delta-sigma Data Converters. ISBN 0-87942-285-8. 
  • Mingliang Liu (2006). Demystifying Switched-Capacitor Circuits. ISBN 0-7506-7907-7. 
  • S. Norsworthy, R. Schreier, G. Temes (1997). Delta-Sigma Data Converters. ISBN 0-7803-1045-4. 
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