CAS latency

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CAS latency (CL) is the delay time which elapses between the moment a memory controller tells the memory module to access a particular column in a selected row, and the moment the data from the given array location is available on the module's output pins.

In asynchronous DRAM, the interval is specified in nanoseconds. In synchronous DRAM, the interval is specified in clock cycles, and must be multiplied by the cycle time (i.e. divided by the clock frequency) to convert to nanoseconds.

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[edit] DRAM Operation Background

Dynamic RAM is arranged in a rectangular array. Each row is selected by a horizontal word line, which switches on a row's worth of transistors, connecting each storage capacitor to its corresponding vertical bit line. Each bit line (actually, there are a pair, but that is not relevant here) connects to a sense amplifier that amplifies the small voltage change produced by the storage capacitor to a large signal that can be output from the DRAM chip and is driven back up the bit line to refresh the row.

When no word line is active, the array is idle and the bit lines are held in a precharged state, with a voltage halfway between high and low, ready to be deflected one way or another by the storage capacitor.

When a row address is presented to the array (accompanied by the row address strobe or /RAS), the corresponding row is activated and copied into the sense amplifiers. At this point, the row is "open" and portions can be read out, selected by the column address.

The delay between presenting a column address to the DRAM (accompanied by the column address strobe or /CAS) and receiving the corresponding data is the CAS latency.

As an example, a typical 1 GiB DDR2 DIMM might contain eight 1 gigabit DRAM chips, each arranged as 128M×8. Each chip is divided internally into 8 banks of 227=128 Mibit, each a separate DRAM array. Each array contains 214=16384 rows of 213=8192 bits each. One byte of memory (from each chip; 64 bits total from the whole DIMM) is accessed by supplying a 3-bit bank number, a 14-bit row address, and a 10-bit column address.

[edit] Effect on memory access speed

With simple asynchronous DRAM, there is simply a time delay between presenting a column address and receiving the data on the output pins. Modern synchronous DRAMs have a CAS latency measured in clock cycles.

Because they have multiple internal banks, and data can be output from one during access latency for another, the output pins can be kept 100% busy regardless of the CAS latency; the maximum attainable bandwidth is determined solely by the clock speed. However, that only applies if the data to be read is known long enough in advance; if the data being accessed is not predictable, the latency matters. For a completely unknown memory access, the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it. Due to spatial locality, however, it is common to access several words in the same row. In this case, the CAS latency alone determines the elapsed time.

In general, the lower the CAS latency, the better. When comparing latencies at different clock speeds, they must be translated into times to make a sensible comparison; a higher numerical CAS latency can be less time if the clock is faster. Note that memory rated for a certain maximum speed can always be operated at a lower clock rate. The CAS latency can be set lower in such a case.

It is important to remember that CAS latencies are in clock cycles. When using double data rate transfers, there are two transfers per clock cycle, and it is usually the transfer rate that is quoted. The clock cycle rate is half of this. In the table below, data rates are given in million of transfers per second (MT/s), while clock rates are given in MHz, cycles per second.

Another complicating factor is burst transfers. A modern microprocessor might have a cache line size of 64 bytes, requiring 8 transfers from a 64-bit (8 byte) wide memory to fill. The CAS latency only measures the time to transfer the first word of memory; the time to transfer all 8 words depends on the clock rate. Fortunately, the processor does not need to wait for all 8 words; the burst is usually sent in critical word first order, and the first critical word can be used by the microprocessor immediately.

For example, it is common for PC100 SDRAM to have a CAS latency of 2 cycles, or 20 ns (at 10 ns/cycle), while PC133 SDRAM usually requires a CAS latency of 3 cycles, totalling 22.5 ns (at 7.5 ns/cycle). However, transferring a 4-word burst requires an additional 3 cycles. The total time is then 5 cycles or 50 ns for the PC100, and 6 cycles or 45 ns for the PC133.

Memory timing examples (CAS latency only)
Type Data rate Bit time Command rate Cycle time CL First word Fourth word Eighth word
PC100 100 MT/s 10 ns 100 MHz 10 ns 2 20 ns 50 ns 90 ns
PC133 133 MT/s  7.5 ns 133 MHz  7.5 ns 3 22.5 ns 45 ns 75 ns
DDR-333 333 MT/s  3 ns 166 MHz  6 ns 2.5 15 ns 24 ns 36 ns
DDR-400 400 MT/s  2.5 ns 200 MHz  5 ns 3 15 ns 22.5 ns 32.5 ns
2.5 12.5 ns 20 ns 30 ns
2 10 ns 17.5 ns 27.5 ns
DDR2-667 667 MT/s  1.5 ns 333 MHz  3 ns 5 15 ns 19.5 ns 25.5 ns
DDR2-800 800 MT/s  1.25 ns 400 MHz  2.5 ns 6 15 ns 18.75 ns 23.75 ns
5 12.5 ns 16.25 ns 21.25 ns
DDR3-1333 1333 MT/s  0.75 ns 666 MHz  1.5 ns 9 13.5 ns 15.75 ns 18.75 ns
6  9 ns 11.25 ns 14.25 ns
DDR3-1375 1375 MT/s  0.73 ns 687 MHz  1.5 ns 5  7.27 ns  9.45 ns 12.36 ns
DDR3-1600 1600 MT/s  0.625 ns 800 MHz  1.25 ns 9 11.25 ns 13.125 ns 15.625 ns
8 10 ns 11.875 ns 14.375 ns
7  8.75 ns 10.625 ns 13.125 ns

Notice how the time to the first bit (CAS latency in nanoseconds) has improved only slowly through DRAM generations, but the time to read an 8-word burst has improved dramatically.

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